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dual, 200 ma, high performance rf ldo with load switch adp5030 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features input voltage range: 2.5 v to 5.5 v dual, 200 ma low dropout voltage regulators tiny, 16-ball, 1.6 mm 1.6 mm wlcsp initial accuracy: 0.7% stable with 1 f ceramic output capacitors overcurrent and thermal protection high psrr 76 db up to 1 khz 70 db at 10 khz 60 db at 100 khz 40 db at 1 mhz low output noise 27 v rms typical output noise at v outx = 1.2 v 50 v rms typical output noise at v outx = 2.8 v excellent transient response low dropout voltage: 175 mv at 200 ma load 60 a typical ground current at no load, both ldos enabled guaranteed 200 ma output current per regulator load switch with low rds on of 100 m at 1.8 v high-to-low voltage and low-to-high voltage level shifting logic ?40c to +125c junction temperature applications rf subsystems gps devices general description the adp5030 combines two high performance, low dropout (ldo) voltage regulators, a low rds on load switch, and level shifting logic in a tiny, 16-ball, 1.6 mm 1.6 mm wlcsp to meet demanding performance and board space requirements. the low quiescent current, low dropout voltage, and wide input voltage range of the adp5030 ldos extend the battery life of portable devices. the adp5030 ldos maintain power supply rejection greater than 60 db for frequencies as high as 100 khz while operating with a low headroom voltage. the adp5030 can be configured in two different activation modes for ldo2 and the load switch; these modes are selected by a dedicated pin (msel). functional block diagram c1 1f c2 1f c3 1f c4 0.1f c5 2.2f ldo2 load switch ldo1 vin2 vin3 vin3 vin3 gpin1 gpout1 gpout2 gpout3 vout1 gpin2 gpin3 vout2 vout3 vin1 en1 vin2 en2 vin3 gnd power supply and processor gpo0_1v8 gpo1_1v8 gpi0_1v8 gpo2_1v8 gpo4_1v8 vdd v1_8dig 1.8v input/output system peripheral module gpi0_1v2 gpi1_1v2 vbb gpo0_1v2 vaux vio 1.2v input/output system msel adp5030 07893-001 figure 1.
adp5030 rev. b | page 2 of 2 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? input and output capacitor, recommended specifications .. 4 ? absolute maximum ratings ............................................................ 5 ? thermal data ................................................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 13 ? applications information .............................................................. 14 ? ldo2 and load switch activation logic ............................... 15 ? sequencing .................................................................................. 15 ? capacitor selection .................................................................... 15 ? undervoltage lockout ............................................................... 16 ? enable feature ............................................................................ 16 ? current-limit and thermal overload protection ................. 17 ? thermal considerations ............................................................ 17 ? pcb layout considerations ...................................................... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 11/09rev. a to rev. b changes to figure 36 and figure 37 captions ............................ 14 9/09rev. 0 to rev. a changes to output noise parameter; level shifter, gpout1 output logic low and gpout2, gpout3 output logic low parameters, table 1 ........................................................................... 3 changes to table 3 and table 4 ....................................................... 5 changes to input and output capacitor properties section .... 15 6/09revision 0: initial version
adp5030 rev. b | page 3 of 3 specifications v in1 = (v out2 + 0.5 v) or 2.5 v (whichever is greater), v in1 v in2 v in3 , i out1 = i out2 = 10 ma, t a = 25c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit input voltage range 1 v in1 t j = ?40c to +125c 2.5 5.5 v v in2 t j = ?40c to +125c 1.1 1.8 3.6 v v in3 t j = ?40c to +125c 1.1 v in2 v operating supply current with both regulators on i gnd 60 a i out1 , i out2 = 0 a 60 a i out1 , i out2 = 0 a, t j = ?40c to +125c 120 a i out1 , i out2 = 10 ma 70 a i out1 , i out2 = 10 ma, t j = ?40c to +125c 140 a i out1 , i out2 = 200 ma 120 a i out1 , i out2 = 200 ma, t j = ?40c to +125c 220 a shutdown current en1 = gnd, gpin2 = gpin1 = v ih from vin1 pin i in1-sd v in1 = 5.5 v, t j = ?40c to +125c 0.4 2.0 a from vin2 pin i in2-sd v in2 = 1.8 v, t j = ?40c to +85c 0.4 2.0 a from vin3 pin i in3-sd v in3 = 1.2 v, t j = ?40c to +125c 0.2 1.5 a fixed output voltage accuracy v out1 , v out2 ?0.7 +0.7 % 100 a < i out1 , i out2 < 200 ma, v in1 = (v out2 + 0.5 v) to 5.5 v, t j = ?40c to +125c ?2.0 +1 % line regulation ?v out /?v in v in1 = (v out2 + 0.5 v) to 5.5 v 0.01 %/v v in1 = (v out2 + 0.5 v) to 5.5 v, t j = ?40c to +125c ?0.03 +0.03 %/v load regulation ?v out /?i out i out1 , i out2 = 1 ma to 200 ma 0.001 %/ma i out1 , i out2 = 1 ma to 200 ma, t j = ?40c to +125c 0.003 %/ma dropout voltage 2 v dropout v out2 = 2.8 v i out1 , i out2 = 10 ma 9 mv i out1 , i out2 = 10 ma, t j = ?40c to +125c 13 mv i out1 , i out2 = 200 ma 175 mv i out1 , i out2 = 200 ma, t j = ?40c to +125c 250 mv start-up time 3 t start-up v out2 = 2.8 v 240 s v out1 = 1.2 v 120 s current-limit threshold 4 i limit1 , i limit2 240 300 440 ma load switch output current i out3 500 ma thermal shutdown thermal shutdown threshold ts sd t j rising 155 c thermal shutdown hysteresis ts sd-hys 15 c en1, msel inputs en1, msel input logic high v ih1 2.5 v v in1 5.5 v 1.2 v en1, msel input logic low v il1 2.5 v v in1 5.5 v 0.4 v en1, msel input leakage current i leakage1 en1 = msel = v in1 or gnd 0.2 a en1 = msel = v in1 or gnd, t j = ?40c to +125c 1 a en2 input en2 input logic high v ih2 1.2 v v in2 3.6 v 0.65 v in2 v en2 input logic low v il2 1.2 v v in2 3.6 v 0.35 v in2 v en2 input leakage current i leakage2 en2 = v in2 or gnd 0.2 a en2 = v in2 or gnd, t j = ?40c to +125c 1 a undervoltage lockout (v in1 ) uvlo input voltage rising uvlo rise 2.45 v input voltage falling uvlo fall 2.2 v hysteresis uvlo hys 100 mv output noise out noise 10 hz to 100 khz, v in1 = 5 v, v outx = 2.8 v 50 v rms 10 hz to 100 khz, v in1 = 3.6 v, v outx = 1.2 v 27 v rms
adp5030 rev. b | page 4 of 4 parameter symbol test conditions/comments min typ max unit power supply rejection ratio psrr v in1 = 2.5 v, v out1 = 1.2 v, i out = 100 ma 100 hz 76 db 1 khz 76 db 10 khz 70 db 100 khz 60 db 1 mhz 40 db v in1 = 3.8 v, v out2 = 2.8 v, i out = 100 ma 100 hz 68 db 1 khz 68 db 10 khz 68 db 100 khz 60 db 1 mhz 40 db load switch vin2 to vout3 resistance rds on i load = 200 ma, en2 = v ih2 , msel = gpin1 = gnd v in2 = 3.6 v 70 m v in2 = 2.5 v 80 m v in2 = 1.8 v 100 130 m v in2 = 1.8 v, t j = ?40c to +125c 160 m turn-on times v in2 = 1.8 v, i load = 100 ma, c load = 0.1 f, en2 = v ih2 , msel = gpin1 = gnd turn-on delay time t on_dly en2 rising to 10% of tu rn-on value 5 15 s turn-on rise time t on_rise v out3 rising from 10% to 90% of turn-on value 8 12 s level shifter v in1 = 3.6 v, 1.2 v v in3 3.6 v, t j = ?40c to +125c gpin1 input logic high v ih 0.65 v in3 v gpin1 input logic low v il 0.35 v in3 v gpout1 output logic high v oh i oh = 2 ma, v in2 = 1.8 v 1.6 v gpout1 output logic low v ol i ol = 1 ma, v in2 = 1.8 v 0.16 v gpout1 output logic low v ol i ol = 2 ma, v in2 = 1.8 v 0.31 v gpin1 to gpout1 propagation delay t phl , t plh c load = 30 pf, r load = 1 m, v in2 = 1.8 v 20 ns gpin2, gpin3 input logic high v ih 0.65 v in3 v gpin2, gpin3 input logic low v il 0.35 v in3 v gpout2, gpout3 output logic high v oh i oh = 2 ma, v in3 = 1.2 v 0.95 v gpout2, gpout3 output logic low v ol i ol = 1 ma, v in3 = 1.2 v 0.17 v i ol = 2 ma, v in3 = 1.2 v 0.33 v gpin2, gpin3 to gpout2, gpout3 propagation delay t phl , t plh c load = 30 pf, r load = 1 m 20 ns gpin1, gpin2, gp in3 input leakage current i leakage-gpin gpin1, gpin2, gpin3 = v in3 or gnd, t a = 25c 0.1 a gpin1, gpin2, gpin3 = v in3 or gnd 1 a 1 v in2 minimum supply voltage is 1.1 v or v in3 , whichever is greater. v in2 maximum supply voltage is 3.6 v or v in1 , whichever is smaller. 2 dropout voltage is the input-to-output voltage differential when the input voltage is set to the nominal output voltage. it ap plies only to output voltages above 2.5 v. 3 start-up time is defined as the time between the rising edge of en1 to v out1 being at 90% of its nominal value. 4 current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output capacitor, recommended specifications table 2. parameter symbol test conditions min typ max unit minimum input and output capacitance (ldo1, ldo2) 1 c min t a = C40c to +125c 0.70 f capacitor esr r esr t a = C40c to +125c 0.001 1 1 the minimum input and output capacitance should be greater than 0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during capacitor selection to en sure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with this ldo.
adp5030 rev. b | page 5 of 5 absolute maximum ratings table 3. parameter rating vin1, en1, msel to gnd ?0.3 v to +6.5 v vout1, vout2 to gnd ?0.3 v to v in1 vin2, vin3, en2, gpin1, gpin2, gpin3 to gnd ?0.3 v to +3.6 v vout3, gpout1 to gnd ?0.3 v to v in2 gpout2, gpout3 to gnd ?0.3 v to v in3 storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp5030 can be damaged when the junction temperature limits are exceeded. monitoring ambient tempera- ture does not guarantee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor pcb thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the following formula: t j = t a + ( p d ja ) the junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4-inch 3-inch circuit board. refer to jedec jesd51-9 for detailed information about board construction. for more information, see the an-617 application note, microcsp tm wafer le vel chip scale package at www.analog.com . jb is the junction-to-board thermal characterization parameter with units of c/w. the jb of the package is based on modeling and calculation using a 4-layer board. the jedec jesd51-12 document, guidelines for reporting and using electronic package thermal information , states that thermal characterization param- eters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than through a single path, as in thermal resistance ( jb ). there- fore, jb thermal paths include convection from the top of the package, as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and the power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) refer to the jedec jesd51-8 and jesd51-12 documents for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 16-ball, 0.4 mm pitch wlcsp 66.6 18.5 c/w esd caution
adp5030 rev. b | page 6 of 6 pin configuration and fu nction descriptions top view (ball side down) not to scale 1 a b c d 234 ball a1 indicator vout3 vin2 gpout3 vin3 en2 gpin2 gpin1 gnd vout2 vin1 vout1 en1 msel gpin3 gpout2 gpout1 07893-002 figure 2. pin configuration, top view table 5. pin function descriptions pin no. mnemonic description a1 vout3 load switch output. a2 msel select activation logic for ldo2 and load switch. connect msel to gnd to select mode 1. connect msel to vin1 to select mode 2. a3 en2 enable vout2 and vout3. when msel is set to logic 0 (mode 1), vout2/vout3 activation is the logic nor of en2 with gpin1. when msel is set to logic 1 (mode 2), vout2/vout3 ac tivation is the logic and of en2 with not gpin1. a4 vout2 ldo2 output. b1 vin2 digital supply input. b2 gpin3 input to level shifter. b3 gpin2 input to level shifter. b4 vin1 system supply. c1 gpout3 output of level shifter. c2 gpout2 output of level shifter. c3 gpin1 input to level shifter. c4 vout1 ldo1 output. d1 vin3 logic translator supply. d2 gpout1 output of level shifter. d3 gnd ground. d4 en1 enable vout1.
adp5030 rev. b | page 7 of 7 typical performance characteristics v in1 = 3.3 v, v out1 = 1.2 v, v out2 = 2.8 v, i out1 = i out2 = 10 ma, c in = c out1 = c out2 = 1 f, t a = 25c, unless otherwise noted. 1.190 1.210 1.205 1.200 1.195 ?40 ?5 25 85 125 v out1 (v) junction temperature (c) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 07893-003 figure 3. v out1 output voltage vs. junction temperature 2.780 2.785 2.790 2.795 2.800 2.805 2.810 2.815 2.820 ?40?5 25 85125 junction temperature (c) v out2 (v) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 07893-004 figure 4. v out2 output voltage vs. junction temperature 0 20 40 60 80 100 120 140 ?40?52585125 junction temperature (c) ground current (a) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 07893-005 figure 5. ground current vs. junction temperature, v out1 loaded 0 20 40 60 80 100 120 140 ?40?52585125 junction temperature (c) ground current (a) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 07893-006 figure 6. ground current vs. junction temperature, v out2 loaded 0 20 40 60 80 100 140 120 160 junction temperature (c) ground current (a) load = 10a load = 100a load = 1ma load = 10ma load = 100ma load = 200ma 07893-007 ?40?52585125 figure 7. ground current vs. junction temperature, both ldos loaded 0 2 4 6 8 10 12 14 ?50 ?25 0 25 50 75 100 125 junction temperature (c) v in2 shutdown current ( a) 2.5v 2.6v 2.8v 2.9v 3.3v 3.6v 07893-008 figure 8. v in2 shutdown current vs. junction temperature at various input voltages
adp5030 rev. b | page 8 of 8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?50 ?25 0 25 50 75 100 125 v in1 shutdown current ( a) 3.2v 3.3v 3.8v 4.1v 4.7v 5.5v 07893-009 junction temperature (c) figure 9. v in1 shutdown current vs. junction temperature at various input voltages 0 0.2 0.6 0.4 0.8 1.0 1.2 1.4 1.6 ?50 ?25 0 25 50 75 100 125 1.5v 1.8v 1.1v 1.2v 2.5v 3.0v 3.3v 3.6v 07893-010 junction temperature (c) v in3 shutdown current ( a) figure 10. v in3 shutdown current vs. junction temperature at various input voltages 0 25 50 75 100 125 150 175 200 1 10 100 1000 load current (ma) v out2 dropout voltage (mv) 07893-011 figure 11. v out2 dropout voltage vs. load current 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.6 2.7 2.8 2.9 3.0 3.1 v out2 output voltage (v) input voltage v in1 (v) load = 1ma load = 10ma load = 50ma load = 100ma load = 150ma load = 200ma 07893-012 figure 12. v out2 output voltage vs. input voltage (in dropout) and load current 0 20 40 60 80 100 120 140 2.6 2.7 2.8 2.9 3.0 3.1 ground current (a) input voltage v in1 (v) 07893-013 load = 1ma load = 10ma load = 50ma load = 100ma load = 150ma load = 200ma figure 13. ground current for v out2 (in dropout) vs. input voltage and load current 1.2 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.6 2.0 2.4 2.8 3.2 3.6 input voltage v in2 (v) v out3 output voltage (v) load = 5ma load = 500ma 07893-014 figure 14. load switch (v out3 ) output voltage vs. input voltage and load current
adp5030 rev. b | page 9 of 9 0.050 0.075 0.100 0.125 0.150 1 10 100 1k load current (ma) switch resistance ( ? ) t j = ?40c t j = ?5c t j = +25c t j = +85c t j = +125c 07893-015 figure 15. load switch rds on vs. load current, v in2 = 1.8 v 0 0.02 0.01 0.04 0.06 0.03 0.05 0.07 0.08 1 10 100 1k load current (ma) dropout voltage (v) 07893-016 t j = ?40c t j = ?5c t j = +25c t j = +85c t j = +125c figure 16. load switch dropout voltage vs. load current, v in2 = 1.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) load = 200ma load = 100ma load = 10ma load = 1ma v ripple = 50mv v in1 = 3.8v v out2 = 2.8v c out = 1f 07893-017 figure 17. power supply rejection ratio vs. frequency, v in1 = 3.8 v, v out2 = 2.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) load = 200ma load = 100ma load = 10ma load = 1ma v ripple = 50mv v in1 = 3.3v v out1 = 1.2v c out = 1f 07893-018 figure 18. power supply rejection ratio vs. frequency, v in1 = 3.3 v, v out1 = 1.2 v 0.01 0.1 1 10 10 100 1k frequency (hz) 10k 100k noise spectral density (v/ hz) 2.8v 1.2v 07893-019 figure 19. output noise spectral density vs. output voltage, v in1 = 5 v, i load = 10 ma 0 10 20 30 40 50 60 0.001 0.01 0.1 1 10 100 1000 load current (ma) noise (v rms) 2.8v 1.2v 07893-020 figure 20. rms output noise vs. lo ad current and output voltage, v in1 = 5 v
adp5030 rev. b | page 10 of 10 07893-021 ch1 50.0mv ch2 10.0mv b w m 20.0s a ch3 112ma 2 3 1 t 10.20% ch3 100ma ? b w b w v out1 , 50mv/div v out2 , 10mv/div i load1 , 100ma/div figure 21. load transient response, i load1 = 1 ma to 200 ma, i load2 = 1 ma, ch1 = v out1 , ch2 = v out2 , ch3 = i load1 , c out = 1 f 07893-022 ch1 10.0mv ch2 50.0mv b w m 20.0s a ch3 128ma 2 3 1 t 10.20% ch3 100ma ? b w b w v out1 , 10mv/div v out2 , 50mv/div i load2 , 100ma/div figure 22. load transient response, i load1 = 1 ma, i load2 = 1 ma to 200 ma, ch1 = v out1 , ch2 = v out2 , ch3 = i load2 07893-023 ch1 1.00v ch2 10.0mv b w m 4.00s a ch4 ?80.0mv 2 3 1 t 9.800% ch3 10.0mv b w b w v in1 , 1v/div v out1 , 10mv/div v out2 , 10mv/div figure 23. line transient response, v in1 = 4 v to 5 v, i load1 = 1 ma, i load2 = 1 ma, ch1 = v in1 , ch2 = v out1 , ch3 = v out2 07893-024 ch1 1.00v ch2 10.0mv b w m 4.00s a ch4 ?80.0mv 2 3 1 t 9.000% ch3 10.0mv b w b w v in1 , 1v/div v out1 , 10mv/div v out2 , 10mv/div figure 24. line transient response, v in1 = 4 v to 5 v, i load1 = 200 ma, i load2 = 200 ma, ch1 = v in1 , ch2 = v out1 , ch3 = v out2 07893-025 ch1 500mv ch2 1.00v b w m 20.0s a ch2 820mv 2 1 t 10.40% b w v out3 , 500mv/div en2, 1v/div figure 25. load switch typical switching time, i load3 = 500 ma, ch1 = v out3 , ch2 = en2 07893-026 ch1 500mv ch2 1.00v b w m 20.0s a ch2 920mv 1 2 t 10.40% b w v out3 , 500mv/div en2, 1v/div figure 26. load switch typical switching time, i load3 = 100 ma, ch1 = v out3 , ch2 = en2
adp5030 rev. b | page 11 of 11 07893-027 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin1, 500mv/div gpout1, 500mv/div figure 27. gpout1 output vs. gpin1 input, v in2 = 1.8 v, v in3 = 1.2 v, 820 pull-down, msel high, ch1 = gpin1, ch2 = gpout1 07893-028 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin1, 500mv/div gpout1, 500mv/div figure 28. gpout1 output vs. gpin1 input, v in2 = 1.8 v, v in3 = 1.2 v, 820 pull-up, msel high, ch1 = gpin1, ch2 = gpout1 07893-029 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin1, 500mv/div gpout1, 500mv/div figure 29. gpout1 output vs. gpin1 input, v in2 = 1.8 v, v in3 = 1.2 v, 820 pull-down, msel low, ch1 = gpin1, ch2 = gpout1 07893-030 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin1, 500mv/div gpout1, 500mv/div figure 30. gpout1 output vs. gpin1 input, v in2 = 1.8 v, v in3 = 1.2 v, 820 pull-up, msel low, ch1 = gpin1, ch2 = gpout1 07893-131 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin2, 500mv/div gpout2, 500mv/div figure 31. gpout2 output vs. gpin2 input, v in2 = 1.8 v, v in3 = 1.2 v, 600 pull-down, ch1 = gpin2, ch2 = gpout2 07893-032 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin2, 500mv/div gpout2, 500mv/div figure 32. gpout2 output vs. gpin2 input, v in2 = 1.8 v, v in3 = 1.2 v, 600 pull-up, ch1 = gpin2, ch2 = gpout2
adp5030 rev. b | page 12 of 12 07893-033 ch1 500mv ch2 500mv b w m 20.0ns a ch2 700mv 1 2 t 13.40% gpin3, 500mv/div gpout3, 500mv/div figure 33. gpout3 output vs. gpin3 input, v in2 = 1.8 v, v in3 = 1.2 v, 600 pull-down, ch1 = gpin3, ch2 = gpout3 07893-034 ch1 500mv ch2 500mv b w m 20.0ns a ch1 700mv 1 2 t 13.40% gpin3, 500mv/div gpout3, 500mv/div figure 34. gpout3 output vs. gpin3 input, v in2 = 1.8 v, v in3 = 1.2 v, 600 pull-up, ch1 = gpin3, ch2 = gpout3
adp5030 rev. b | page 13 of 13 theory of operation the adp5030 combines two high performance, low dropout voltage regulators and a low rds on high-side load switch that operate from a 2.5 v to 5.5 v supply. level shifting logic that operates from 1.2 v to 3.6 v supplies is also included to facilitate interfacing to system components. the adp5030 can provide up to 200 ma of current from each ldo output and switch up to 500 ma. drawing a low 220 a quiescent current (maximum) at full load makes the adp5030 ideal for battery-operated portable equipment. shutdown current consumption is typically 400 na. optimized for use with small 1 f ceramic capacitors, the adp5030 provides excellent transient performance. vin1 vin2 vout1 vout2 vout3 vin1 gpin2 gpin3 en1 en2 gpin1 gpout1 gpout2 gpout3 vin2 vin3 vin3 vin3 gnd msel a b y sel a b y vin2 vin3 sel vin2 vin2 vin2 vin1 vin1 vin2 vin3 load switch ldo2 ldo1 07893-035 figure 35 . internal block diagram internally, the adp5030 ldos consist of a reference, two error amplifiers, two feedback voltage dividers, and two pmos pass transistors. output current is delivered via the pmos pass transistor, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to flow and decreasing the output voltage. the adp5030 high-side pmos load switch is designed for supply operation from 1.2 v to 3.6 v and is designed for a low on resistance of 100 m at v in2 = 1.8 v. the load switch can carry 500 ma of continuous current. the adp5030 level shifting logic translates logic levels from the control signal operating on vin2 to the circuitry operating on vin3 and vice versa. the adp5030 uses the en1 and en2 pins to control the voutx pins under normal operating conditions. the msel pin is used to select the activation logic for ldo2. when msel is set to logic 0, ldo2 and load switch activation is the logic nor of en2 with gpin1. when msel is set to logic 1, the load switch activation and ldo2 is the logic and of en2 with not gpin1.
adp5030 rev. b | page 14 of 14 applications information 07893-036 c1 1f c2 1f c3 1f c4 0.1f c5 2.2f ldo2 ldo1 vin2 vin3 vin3 vin3 gpin1 gpout1 gpout2 gpout3 vout1 gpin2 gpin3 vout2 vout3 vin1 en1 vin2 en2 vin3 gnd power supply and processor gpo0_1v8 gpo1_1v8 gpi0_1v8 gpo2_1v8 gpo4_1v8 vdd v1_8dig 1.8v input/output system peripheral module gpi0_1v2 gpi1_1v2 vbb gpo0_1v2 vaux vio 1.2v input/output system msel adp5030 load switch figure 36. application diagram (msel low) c1 1f c2 1f c3 1f c4 0.1f c5 2.2f ldo2 ldo1 vin2 vin3 vin3 gpin1 gpout1 gpout2 gpout3 vout1 gpin2 gpin3 vout2 vout3 vin1 en1 vin2 en2 vin3 gnd power supply and processor gpo0_1v8 gpo1_1v8 gpi0_1v8 gpo2_1v8 gpo4_1v8 vdd v1_8dig 1.8v input/output system peripheral module gpi0_1v2 gpi1_1v2 vbb gpo0_1v2 vaux vio 1.2v input/output system msel adp5030 07893-037 vin3 load switch figure 37. application diagram (msel high)
adp5030 rev. b | page 15 of 15 ldo2 and load switch activation logic the activation logic for ldo2 and the load switch is selected through the msel pin. when msel is set to logic 0, ldo2 and load switch activation is the logic nor of en2 with gpin1. when msel is set to logic 1, ldo2 and load switch activation is the logic and of en2 with not gpin1 (see table 6 ). in both modes, vin3 is a dedicated input for the logic translators. table 6. truth table for ldo2 and load switch activation msel en2 gpin1 ldo2 state load switch state 0 0 0 on closed 0 1 0 off off 0 0 1 off off 0 1 1 off off 1 0 0 off off 1 1 0 on closed 1 0 1 off off 1 1 1 off off sequencing the input supply voltage v in1 must be present before applying v in2 and v in3 . during a thermal shutdown event, ldo1, ldo2, and the load switch output turn off and are placed in a high impedance state. when the die temperature decreases below the recovery thresh- old, ldo1, ldo2, and the load switch output turn on if the respective enabling signal is still active. capacitor selection output capacitor the adp5030 ldos are designed for operation with small, space-saving ceramic capacitors, but the part functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 or less is recommended to ensure the stability of the adp5030. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp5030 to large changes in load current. figure 21 shows the transient response for an output capacitance value of 1 f. input bypass capacitor connecting a 1 f capacitor from vinx to gnd reduces the circuit sensitivity to the pcb layout, especially when long input traces or high source impedance are encountered. if an output capacitance greater than 1 f is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitor can be used with the adp5030, as long as the capacitor meets the minimum capaci- tance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. figure 38 shows the capacitance vs. voltage bias characteristics of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera- ture range and is not a function of package size or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 02 4681 voltage bias (v) capacitance (f) 0 07893-031 figure 38. capacitance vs. voltage bias characteristics equation 1 can be used to determine the worst-case capacitance accounting for capacitor variation over temperature, compo- nent tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol) (1) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 0.94 f at 1.8 v, as shown in figure 38 . substituting these values into equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp5030, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
adp5030 rev. b | page 16 of 16 undervoltage lockout the adp5030 has an internal undervoltage lockout circuit on v in1 that disables the inputs and outputs to the ldos and the load switch when the input voltage is less than approximately 2.2 v. this ensures that the inputs and outputs of the adp5030 behave in a predictable manner during power-up. enable feature the adp5030 uses the enx pins to enable and disable the voutx pins under normal operating conditions. as shown in figure 39 and figure 40 , when a rising voltage on enx crosses the active threshold, voutx turns on. when a falling voltage on enx crosses the inactive threshold, voutx turns off. 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.5 1.0 1.5 2.0 2.5 3.0 07893-039 v out1 (v) v en1 (v) figure 39. typical en1 pin operation 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 v out2 (v) v en2 (v) 07893-040 figure 40. typical en2 pin operation as shown in figure 39 and figure 40 , the enx pins have built-in hysteresis. this prevents on/off oscillations that can occur due to noise on the enx pins as they pass through the threshold points. the active/inactive thresholds of the enx pin are derived from the vinx voltage. therefore, these thresholds vary with changing input voltage. figure 41 and figure 42 show typical enx active/inactive thresholds when the input voltages vary from minimum to maximum. 0 0.2 0.4 0.6 0.8 1.0 1.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v en1 threshold (v) v in1 (v) 07893-041 en1 active en1 inactive figure 41. typical en1 pin thresholds vs. input voltage 0 0.5 1.0 1.5 2.0 2.5 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v en2 threshold (v) v in2 (v) 07893-042 en2 active en2 inactive figure 42. typical en2 pin thresholds vs. input voltage the adp5030 uses an internal soft start to limit the inrush current when the outputs are enabled. the typical start-up time for a 2.8 v output is approximately 240 s from the time that the enx active threshold is crossed to when the output reaches 90% of its final value. the start-up time for a 1.2 v output is about 120 s. the start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases. figure 43 and figure 44 show the typical start-up times for 1.2 v and 2.8 v outputs, respectively.
adp5030 rev. b | page 17 of 17 07893-043 ch1 1.0v ch2 1.00v b w m 40.0s a ch2 600mv 1 2 t 13.40% b w waveform intensity: 5% v en1 (v) v out1 (v) figure 43. typical start-up time, v out1 = 1.2 v 07893-044 ch1 1.00v ch2 1.00v b w m 40.0s a ch2 600mv 1 2 t 13.40% b w waveform intensity: 5% v en2 (v) v out2 (v) figure 44. typical start-up time, v out2 = 2.8 v current-limit and thermal overload protection the adp5030 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. the adp5030 is designed to reach current limit when the output load reaches 300 ma (typical). when the output load exceeds 300 ma, the output voltage is reduced to maintain a constant current limit. the load switch is not current-limited so care must be taken to ensure that the output of the load switch is not shorted to ground under any conditions. in the event of a short to ground, the load switch current is limited by the maximum output current of the source. thermal overload protection is built in, which limits the junc- tion temperature to a maximum of 155c (typical). under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature begins to rise above 155c, the output is turned off, reducing the output current to 0 ma. when the junction temperature drops below 140c, the output is turned on again and the output current is restored to its nominal value. consider the case where a hard short from voutx to gnd occurs. at first, the adp5030 reaches current limit, so that only 300 ma is conducted into the short. if self-heating of the junction is great enough to cause its temperature to rise above 155c, thermal shutdown is activated, turning off the output and reducing the output current to 0 ma. as the junction temperature cools and drops below 140c, the output turns on and conducts 300 ma into the short, again causing the junction temperature to rise above 155c. this therma l oscillation between 140c and 155c causes a current oscillation between 0 ma and 300 ma that continues as long as the short remains at the output. current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125c. thermal considerations due to high efficiency, the adp5030 does not dissipate a lot of heat in most applications. however, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum specified junction temperature of 125c. when the junction temperature exceeds 155c, the converter enters thermal shutdown. it recovers only after the junction temperature has decreased below 140c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera- ture rise of the package due to power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp5030 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja value is dependent on the package assembly compounds used and the amount of copper to which the pins of the package are soldered on the pcb. table 7 shows typical ja values for the adp5030 for various pcb copper sizes. table 7. typical ja values copper size (mm 2 ) ja (c/w) 0 1 200 50 173 100 135 300 95 500 76 1 device soldered to minimum size pin traces.
adp5030 rev. b | page 18 of 18 the junction temperature of the adp5030 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to t j = t a + {[(v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c. figure 45 through figure 49 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of pcb copper. in cases where the board temperature is known, the thermal characterization parameter jb can be used to estimate the junction temperature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and the power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical jb value for the 16-ball wlcsp is 18.5c/w. 25 35 45 55 65 75 85 95 105 115 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 junction temperature (c) total power dissipation (w) 07893-045 max junction temperature 500mm 2 100mm 2 0mm 2 figure 45. junction temperature vs. total power dissipation, t a = 25c 50 60 70 80 90 100 110 120 130 140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 junction temperature (c) total power dissipation (w) 07893-046 500mm 2 100mm 2 0mm 2 max junction temperature figure 46. junction temperature vs. total power dissipation, t a = 50c 65 75 85 95 105 115 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 junction temperature (c) total power dissipation (w) 07893-047 500mm 2 100mm 2 0mm 2 max junction temperature figure 47. junction temperature vs. total power dissipation, t a = 65c 85 95 105 115 125 135 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 junction temperature (c) total power dissipation (w) 07893-048 500mm 2 100mm 2 0mm 2 max junction temperature figure 48. junction temperature vs. total power dissipation, t a = 85c
adp5030 rev. b | page 19 of 19 0 20 40 60 80 120 100 140 0 0.5 1.0 2.0 1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 junction temperature (c) total power dissipation (w) 07893-049 t b = 25c t b = 50c t b = 65c t b = 85c max junction temperature pcb layout considerations heat dissipation from the package can be improved by increas- ing the amount of copper attached to the pins of the adp5030. however, as shown in table 7 , a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the vinx and gnd pins. place the output capacitors as close as possible to the voutx and gnd pins. use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. figure 49. junction temperature vs. total power dissipation and board temperature 07893-050 figure 50. example of pcb layout, top side
adp5030 rev. b | page 20 of 20 102108-a outline dimensions 0.66 0.60 0.54 1.60 1.56 sq 1.52 a b c d 0.43 0.40 0.37 1 2 3 4 bottom view (ball side up) top view (ball side down) 0.23 0.20 0.17 0.28 0.26 0.24 ball 1 identifier seating plane 0.05 nom coplanarity 0.40 ref figure 51. 16-ball wafer level chip scale package [wlcsp] (cb-16-6) dimensions show in millimeters ordering guide model temperature range output voltages (v) 1 package description package option branding ADP5030ACBZ-1228R7 2 ?40c to +125c 1.2 v, 2.8 v 16-ball wafer level chip scale package [wlcsp] cb-16-6 l9k 1 for additional voltage options, contact a local sales or distribution representative . 2 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07893-0-11/09(b)

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